1. Technical Field
Embodiments of the present disclosure generally relate to semiconductor devices and semiconductor systems including the same.
2. Related Art
Semiconductor devices may execute a write operation to store data therein and may execute a read operation to output the data stored therein. In order to execute the write operation or the read operation, the semiconductor devices may selectively enable a word line using a row address signal to create a row path or may turn on a switching element coupled between a sense amplifier and an input/output (I/O) line using a column selection signal generated by a column address signal to create a column path.
Each of the semiconductor devices may be designed to include a plurality of I/O lines for outputting data. During a read operation, each sense amplifier may sense and amplify a voltage difference (ΔV) between a pair of I/O lines selected by the column address signal to output the data.
During the read operation of the semiconductor device, at least one of the plurality of I/O lines may be selected by the column address signal while the remaining I/O lines may be non-selected or may not be selected. In such a case, a loading capacitance between the selected I/O line and the non-selected I/O lines adjacent thereto may degrade the function of the sense amplifier. This degradation may lead to an increase in the data access times of the semiconductor device.